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1 ? fn6482.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2008, 2009. all rights reserved all other trademarks mentioned are the property of their respective owners. isl6334, isl6334a vr11.1, 4-phase pwm controller with light load efficiency enhancement and load current monitoring features the isl6334, isl6334a control microprocessor core voltage regulation by driving up to 4 interleaved synchronous-rectified buck channels in parallel. this multiphase architecture results in multiplying channel ripple frequency and reducing input and output ripple currents. lower ripple results in fewer components, lower cost, reduced power dissipation, and smaller implementation area. microprocessor loads can generate load transients with extremely fast edge rates and requires high efficiency at light load. the isl6334, isl6334a utilizes intersil?s proprietary active pulse positioning (app), adaptive phase alignment (apa) modulation scheme, active phase adding and dropping to achieve and maintain the extremely fast transient response with fewer output capacitors and high efficiency from light to full load. the isl6334, isl6334a is designed to be completely compliant with intel vr11.1 specifications. it accurately reports the load current via imon pin to the microprocessor, which sends an active low psi# signal to the controller at low power mode. the controller then enters 1- or 2-phase operation with diode emulation option to reduce magnetic core and switching losses, yielding high efficiency at light load. after the psi# signal is de-asserted, the dropped phase(s) are added back to sustain heavy load transient response and efficiency. today?s microprocessors require a tightly regulated output voltage position versus load current (droop). the isl6334, isl6334a senses the output current continuously by utilizing patented techniques to measure the voltage across the dedicated current sense resistor or the dcr of the output inductor. the sensed current flows out of fb pin to develop the precision voltage drop across the feedback resistor for droop control. current sensing circ uits also provide the needed signals for channel-current balancing, average overcurrent protection and individual phase current limiting. an ntc thermistor?s temperature is sensed via tm pin and internally digitized for thermal monitoring and for integrated thermal compensation of the current sense elements. a unity gain, differential amplifier is provided for remote voltage sensing and completely elimi nates any potential difference between remote and local grounds. this improves regulation and protection accuracy. the threshold-sensitive enable input is available to accurately coordinate the start-up of the isl6334, isl6334a with any other voltage rail. dynamic-vid? technology allows seamless on-the-fly vid changes. the offset pin allows accurate volt age offset settings that are independent of vid setting. features ? intel vr11.1 compliant ? proprietary active pulse po sitioning (app) and adaptive phase alignment (apa) modulation scheme ? proprietary active phase adding and dropping with diode emulation scheme for high light load efficiency ? precision multiphase core voltage regulation - differential remote voltage sensing - 0.5% closed-loop system accuracy over load, line and temperature - bi-directional, adjustable reference-voltage offset ? precision resistor or dcr differential current sensing - accurate load-line (droop) programming - accurate channel-current balancing - accurate load current monitoring via imon pin ? microprocessor voltag e identification input - dynamic vid? technology for vr11.1 requirement - 8-bit vid, vr11 compatible ? average overcurrent protecti on and channel current limit ? precision overcurrent protection on imon pin ? thermal monitoring and overvoltage protection ? integrated programmable temperature compensation ? integrated open se nse line protection ? 1- to 4-phase operation, coupled inductor compatibility ? adjustable switching frequency up to 1mhz per phase ? package option - qfn compliant to jedec pub95 mo-220 qfn - quad flat no leads - product outline ? pb-free (rohs compliant) data sheet may 28, 2009
2 fn6482.1 may 28, 2009 pinout isl6334, isl6334a (40 ld qfn) top view ordering information part number (note) part marking temp. (c) package (pb-free) pkg. dwg. # isl6334irz* isl6334 irz -40 to +85 40 ld 6x6 qfn l40.6x6 isl6334airz* 6334a irz -40 to +85 40 ld 6x6 qfn l40.6x6 isl6334crz* isl6334 crz 0 to +70 40 ld 6x6 qfn l40.6x6 isl6334acrz* 6334a crz 0 to +70 40 ld 6x6 qfn l40.6x6 *add ?-t? suffix for tape and reel. please refe r to tb347 for details on reel specifications. note: these intersil pb-free plastic packa ged products employ special pb-free material sets, molding compounds/die attach materi als, and 100% matte tin plate plus anneal (e3 termination fi nish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements o f ipc/jedec j std-020. vid5 vid4 vid3 vid2 vid1 psi# imon vid0 tm vr_rdy vr_fan vr_hot fs vid7 en_vtt en_pwr ofs vid6 vdiff vcc pwm3 isen3- isen3+ isen1+ isen1- pwm1 pwm4 isen4- isen4+ isen2+ isen2- tcomp vsen rgnd ss pwm2 fb dac ref comp 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 gnd isl6334, isl6334a
3 fn6482.1 may 28, 2009 controller and driver recommendation controller comments isl6334 when psi# is asserted low, the remained channel transmits a special pwm protocol that can be recognized only by the dedi cated vr11.1 drivers isl6622/isl6620 for diode emulation (dcm) o peration. the dropped channel remains in tri-state. isl6334a when psi# is asserted low, the remained channel transmits normal ccm pwm that can be recognized by any intersil driver such as isl6612/isl6614, isl6596, isl6610, and even isl6622/isl6620. the dropped channel remains in tri-state. driver gate drive voltage # of gate drives diode emulation (de) gate drive drop (gvot) comments isl6622 12v dual yes yes for psi# channel and it s coupled channel in coupled inductor applications or all channels isl6622a, isl6622b 12v dual yes no for psi# channel and its coupled channel in coupled inductor applications or all channels. isl6620, isl6620a 5v dual yes no for psi# channel and its coupled channel in coupled inductor applications or all channels isl6612, isl6612a 12v dual no no for drop ped phases or all c hannels with isl6634a isl6596 5v dual no no for dropped phases or all channels with isl6634a isl6614, isl6614a 12v quad no no for drop ped phases or all c hannels with isl6634a isl6610, isl6610a 5v quad no no for drop ped phases or all c hannels with isl6634a note: note: intersil 5v and 12v drivers are mostly pin-to-pin co mpatible and allow dual footprint layout to optimize mosfet sele ction and efficiency. dual = one synchronous channel; quad = two synchronous channels. isl6334, isl6334a
4 fn6482.1 may 28, 2009 isl6334 and isl6334a block diagram - + x1 rgnd vsen vdiff - + vr_rdy +175mv ofs ref dac psi# fb - + comp offset 1 n imon vr_hot vr_fan tm tcomp temperature compensation vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 dynamic vid d/a isen1+ isen1- isen2+ isen2- isen3+ isen3- isen4+ isen4- channel current sense i_trip channel current balance and peak current limit e/a ovp 0.875 - + power-on reset (por) 0.875 - + soft-start and fault logic en_vtt en_pwr n n fs ss gnd pwm2 pwm1 pwm3 pwm4 thermal monitor temperature compensation gain adjust channel detect 1.11v - + ocp - + ocp app and apa modulator app and apa modulator app and apa modulator app and apa modulator clock and ramp generator 1.11v isl6334, isl6334a
5 fn6482.1 may 28, 2009 typical application: 4-phase vr with integrat ed thermal compensatio n, psi# (de and gvot) ref dac vcc comp fb imon vdiff vsen rgnd en_vtt vtt vr_rdy vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 psi# +5v tm tcomp ofs fs ss gnd p load +5v en_pwr isl6334 +5v isen1- isen1+ pwm1 isen2- isen2+ pwm2 isen3- isen3+ pwm3 isen4- isen4+ pwm4 vr_fan vr_hot ntc +12v vcc pvcc pwm boot ugate phase lgate gnd vin +12v vcc pvcc pwm boot ugate phase lgate gnd vin +12v vcc pvcc pwm boot ugate phase lgate gnd vin +12v vcc pvcc pwm boot ugate phase lgate gnd vin ntc: nths0805n02n6801, 6.8k , vishay vin +5v isl6612 driver isl6612 driver isl6612 driver isl6622 driver isl6334 isl6334, isl6334a
6 fn6482.1 may 28, 2009 isl6334, isl6334a typical application - 4-phase vr with 1-phase psi# and without diode emulation and gvot) ref dac vcc comp fb vdiff vsen rgnd en_vtt vtt vr_rdy vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 psi# +5v tm tcomp ofs fs ss p load +5v isl6334 +5v isen1- isen1+ pwm1 isen2- isen2+ pwm2 isen3- isen3+ pwm3 isen4- isen4+ pwm4 vr_fan vr_hot ntc +12v vcc pvcc pwm boot ugate phase lgate gnd vin +12v vcc pvcc pwm boot ugate phase lgate gnd vin +12v vcc pvcc pwm boot ugate phase lgate gnd vin +12v vcc pvcc pwm boot ugate phase lgate gnd vin imon gnd en_pwr vin +5v ntc: nths0805n02n6801, 6.8k , vishay isl6612 driver isl6612 driver isl6612 driver isl6612 driver isl6334a
7 fn6482.1 may 28, 2009 typical application -vr with external thermal compensation, 2-phase psi# (no de and gvot) ntc o c ref dac vcc comp fb vdiff vsen rgnd en_vtt vtt vr_rdy vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 psi# tm tcomp ofs fs ss p load +5v isl6334 +5v isen1- isen1+ pwm1 isen2- isen2+ pwm2 isen3- isen3+ pwm3 isen4- isen4+ pwm4 vr_fan vr_hot ntc gnd +12v vcc pvcc pwm1 boot1 ugate1 phase1 lgate1 vin pwm2 boot2 ugate2 phase2 lgate2 pgnd vin 12v gnd +12v vcc pvcc pwm1 boot1 ugate1 phase1 lgate1 vin pwm2 boot2 ugate2 phase2 lgate2 pgnd vin 12v imon 5v gnd en_pwr vin +5v 5v ntc: nths0805n02n6801, 6.8k , vishay isl6614 driver isl6614 driver isl6334a isl6334, isl6334a
8 fn6482.1 may 28, 2009 absolute maximum rati ngs thermal information supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6v all pins . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd -0.3v to v cc + 0.3v esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2kv machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200v charged device model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kv operating conditions supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% ambient temperature isl6334acrz, isl6334crz . . . . . . . . . . . . . . . . . . 0c to +70c isl6334irz, isl6334airz. . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (notes 1, 2) ja (c /w) jc (c /w) 40 ld 6x6 qfn package . . . . . . . . . . . 32 2 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379 2. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: vcc = 5v, unless otherwise specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperat ure limits established by characterization and are not production tested. parameter test conditions min typ max units vcc supply current nominal supply vcc = 5vdc; en_pwr = 5vdc; r t = 100k , isen1 = isen2 = isen3 = isen4 = 80a -1620ma shutdown supply vcc = 5vdc; en_pwr = 0vdc; r t = 100k -1417ma power-on reset and enable vcc rising por threshold 4.3 4.4 4.5 v vcc falling por threshold 3.75 3.88 4.0 v en_pwr rising threshold 0.875 0.897 0.920 v en_pwr falling threshold 0.735 0.752 0.770 v en_vtt rising threshold 0.875 0.897 0.920 v en_vtt falling threshold 0.735 0.752 0.770 v reference voltage and dac system accuracy of isl6334crz, isl6334acrz (vid = 1v to 1.6v, t j = 0c to +70c) (note 3, closed-loop) -0.5 - 0.5 %vid system accuracy of isl6334crz, isl6334acrz (vid = 0.5v to 1v, t j = 0c to +70c) (note 3, closed-loop) -5 - 5 mv system accuracy of isl6334irz, isl6334airz (vid = 1v to 1.6v, t j = -40c to +85c) (note 3, closed-loop) -0.6 - 0.6 %vid system accuracy of isl6334irz, isl6334airz (vid = 0.8v to 1v, t j = -40c to +85c) (note 3, closed-loop) -6 - 6 mv system accuracy of isl6334irz, isl6334airz (vid = 0.5v to 0.8v, t j = -40c to +85c) (note 3, closed-loop) -7 - 7 mv vid pull-up after t d3 30 40 50 a vid input low level --0.4v vid input high level 0.8 - - v max dac source current 3.5 - - ma isl6334, isl6334a
9 fn6482.1 may 28, 2009 max dac sink current 100 - - a max ref source/sink current (note 4) 50 - - a pin-adjustable offset voltage at ofs pin offset resistor connected to ground 390 400 415 mv voltage below vcc, offset resistor connected to vcc 1.574 1.60 1.635 v oscillators accuracy of switching frequency setting r t = 100k 225 250 275 khz adjustment range of switching frequency (note 4) 0.08 - 1.0 mhz soft-start ramp rate r ss = 100k (notes 4, 5, 6) - 1.563 - mv/s adjustment range of soft-start ramp rate (note 4) 0.625 - 6.25 mv/s pwm generator sawtooth amplitude (note 4) - 1.5 - v error amplifier open-loop gain r l = 10k to ground (note 4) - 96 - db open-loop bandwidth (note 4) - 80 - mhz slew rate (note 4) - 25 - v/s maximum output voltage 3.8 4.4 4.9 v output high voltage @ 2ma 3.6 - - v output low voltage @ 2ma --1.6v remote-sense amplifier (note 4) bandwidth (note 4) - 20 - mhz output high current vsen - rgnd = 2.5v -500 - 500 a output high current vsen - rgnd = 0.6 -500 - 500 a pwm output sink impedance pwm = low with 1ma load 100 220 300 source impedance pwm = high, forced to 3.7v 200 320 400 psi# input high signal threshold --0.8v low signal threshold 0.4 - - v current sense and overcurrent protection sensed current tolerance isen1 = isen2 = isen3 = isen4 = 40a; cs offset and mirror error included, r isenx = 200 36.5 - 42 a isen1 = isen2 = isen3 = isen4 = 80a; cs offset and mirror error included, r isenx = 200 74 - 83 a overcurrent trip level for average current at normal ccm pwm mode cs offset and mirror error included, r isenx = 200 96 105 117 a overcurrent trip level for average current at psi# mode n = 4, drop to 1 phase - 121 - a peak current limit for individual channel 115 129 146 a imon clamped and ocp trip level 1.085 1.11 1.14 v electrical specifications operating conditions: vcc = 5v, unless otherwise specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperat ure limits established by characterization and are not production tested. (continued) parameter test conditions min typ max units isl6334, isl6334a
10 fn6482.1 may 28, 2009 thermal monitoring and fan control tm input voltage for vr_fan trip 38.7 39.1 39.6 %vcc tm input voltage for vr_fan reset 44.6 45.1 45.5 %vcc tm input voltage for vr_hot trip 32.9 33.3 33.7 %vcc tm input voltage for vr_hot reset 38.7 39.1 39.6 %vcc leakage current of vr_fan with external pull-up resistor connected to vcc - - 5 a vr_fan low voltage with 1.24k resistor pull-up to vcc, i vr_fan = 4ma - - 0.3 v leakage current of vr_hot with external pull-up resistor connected to vcc - - 5 a vr_hot low voltage with 1.24k resistor pull-up to vcc, i vr_hot = 4ma - - 0.3 v vr ready and protection monitors leakage current of vr_rdy with pull-up re sistor externally connected to vcc - - 5 a vr_rdy low voltage i vr_rdy = 4ma - - 0.3 v undervoltage threshold vdiff falling 48 50 52 %vid vr_rdy reset voltage vdiff rising 57 59.6 62 %vid overvoltage protection threshold before valid vid 1.250 1.273 1.300 v after valid vid, the voltage above vid 158 175 190 mv overvoltage protection reset hysteresis - 100 - mv notes: 3. these parts are designed and adjusted for accuracy with all errors in the voltage loop included. 4. limits should be considered typi cal and are not production tested. 5. during soft-start, vdac rises from 0v to 1.1v fi rst and then ramp to vid voltage after receiving valid vid. 6. soft-start ramp rate is determined by the adjustable soft -start oscillator frequency at the speed of 6.25mv per cycle. electrical specifications operating conditions: vcc = 5v, unless otherwise specified. parameters with min and/or max limits are 100% tested at +25c, unless otherwise specified. temperat ure limits established by characterization and are not production tested. (continued) parameter test conditions min typ max units isl6334, isl6334a
11 fn6482.1 may 28, 2009 functional pin description vcc - supplies the power necessary to operate the chip. the controller starts to operate when the voltage on this pin exceeds the rising por threshold and shuts down when the voltage on this pin drops below the falling por threshold. connect this pin directly to a +5v supply. gnd - bias and reference ground for the ic. the bottom metal base of isl6334, isl6334a is the gnd. en_pwr - this pin is a threshold- sensitive enable input for the controller. connecting the 12v supply to en_pwr through an appropriate resistor divider provides a means to synchronize power-up of the controller and the mosfet driver ics. when en_pwr is driven above 0.875v, the isl6334, isl6334a is active depending on status of the en_vtt, the internal por, and pending fault states. driving en_pwr below 0.745v will clear all fault states and prime the isl6334, isl6334a to soft-start when re-enabled. en_vtt - this pin is another th reshold-sensitive enable input for the controller. it?s typically connected to vtt output of vtt voltage regulator in the computer mother board. when en_vtt is driven above 0.875v, the isl6334, isl6334a is active depending on status of the en_pwr, the internal por, and pending fault states. driving en_vtt below 0.745v will clear all fault states and prime the isl6334, isl6334a to soft-start when re-enabled. vdiff, vsen and rgnd - vsen and rgnd form the precision differential remote-sense amplifier. this amplifier converts the differential voltage of the remote output to a single-ended voltage referenced to local ground. vdiff is the amplifier?s output and the input to the regulation and protection circuitr y. connect vsen and rgnd to the sense pins of the remote load. fb and comp - inverting input and output of the error amplifier respectively. fb can be connected to vdiff through a resistor. a properly chosen resistor between vdiff and fb can set the load line (droop), because the sensed current will flow out of fb pin. the droop scale factor is set by the ratio of the isen resistors and the inductor dcr or the dedicated current sense resistor. comp is tied back to fb through an external r-c network to compensate the regulator. dac and ref - the dac pin is the output of the precision internal dac reference. the re f pin is the positive input of the error amplifier. in typical applications, a 1k , 1% resistor is used between dac and ref to generate a precision offset voltage. this voltage is proportional to the offset current determined by the offset resistor from ofs to ground or vcc. a capacitor is used between ref and ground to smooth the voltage transition during dynamic vid? operations. vr_rdy - vr_rdy indicates that so ft-start has completed and the output voltage is wit hin the regulated range around vid setting. it is an open-dr ain logic output. when ocp or ovp occurs, vr_rdy will be pulled to low. it will also be pulled low if the output voltage is below the undervoltage threshold. ofs - the ofs pin can be used to program a dc offset current, which will generate a dc offset voltage between the ref and dac pins. the offset current is generated via an external resistor and precision internal voltage references. the polarity of the offset is selected by connecting the resistor to gnd or vcc. for no offset, the ofs pin should be left unterminated. tcomp - temperature compensation scaling input. the voltage sensed on the tm pin is utilized as the temperature input to adjust i droop and the overcurrent protection limit to effectively compensate for the temperature coefficient of the current sense element. to implement the integrated temperature compensation, a resi stor divider circuit is needed with one resistor being connected from tcomp to vcc of the controller and another resistor being connected from tcomp to gnd. changing the ratio of the resistor values will set the gain of the integrated thermal compensation. when integrated temperature compensation func tion is not used, connect tcomp to gnd. tm - tm is an input pin for the vr temperature measurement. connect this pin through an ntc thermistor to gnd and a resistor to vcc of the controlle r. the voltage at this pin is reverse proportional to the vr temperature. the isl6334, isl6334a monitors the vr temperature based on the voltage at the tm pin and outputs vr_hot and vr_fan signals. vr_hot - vr_hot is used as an indication of high vr temperature. it is an open-drai n logic output. it will be pulled low if the measured vr temperature is less than a certain level, and open when the measured vr temperature reaches a certain level. a external pull-up resistor is needed. vr_fan - vr_fan is an output pin with open-drain logic output. it will be pulled low if the measured vr temperature is less than a certain level, and open when the measured vr temperature reaches a certain level. a external pull-up resistor is needed. pwm1, pwm2, pwm3, pwm4 - pulse width modulation outputs. connect these pins to the pwm input pins of the intersil driver ic. the number of active channels is determined by the state of pwm2, pwm3 and pwm4. tie pwm2 to vcc to configure for 1-phase operation. tie pwm3 to vcc to configure for 2-phase operation. tie pwm4 to vcc to configure for 3-phase operation. in addition, tie psi# to gnd to configure for single phase operation with diode emulation. isen1+, isen1-; isen2+, isen2-; isen3+, isen3-; isen4+, isen4- - the isen+ and isen- pins are current sense inputs to individual differential amplifiers. the sensed current is used for channel current balancing, overcurrent isl6334, isl6334a
12 fn6482.1 may 28, 2009 protection, and droop regulati on. inactive channels should have their respective current sense inputs left open (for example, open isen4+ and isen4- for 3-phase operation). for dcr sensing, connect each isen- pin to the node between the rc sense elements. tie the isen+ pin to the other end of the sense capacitor through a resistor, r isen . the voltage across the sense capacitor is proportional to the inductor current. therefore, t he sense current is proportional to the inductor current and scaled by the dcr of the inductor and r isen . to match the time delay of the in ternal circuit, a capacitor is needed between each isen+ pin and gnd, as described in ?current sensing? on page 14. imon - imon is the output pin of sensed, thermally compensated (if internal thermal compensation is used) average current. the voltage at imon pin is proportional to the load current and the resistor value, and internally clamped to 1.11v plus the remote ground potential difference. if the clamped voltage (1.11v) is triggered, it will initiate the overcurrent shutdown. by choos ing the proper value for the resistor at imon pin, the overcu rrent trip level can be set to be lower than the fixed internal overcurrent threshold. during the dynamic vid, the ocp function of this pin is disable to avoid falsely triggering. tie it to gnd if not used. fs - use this pin to set up the desired switching frequency. a resistor, placed from fs to ground/vcc will set the switching frequency. the relationship between the value of the resistor and the switching frequency will be approximated by equation 3. this pin is also used with ss and psi# pins for phase dropping decoding. see table 1. ss - use this pin to set up the desired start-up oscillator frequency. a resistor placed from ss to ground/vcc will set up the soft-start ramp rate. the relationship between the value of the resistor and the soft-start ramp up time will be approximated by equations 15 and 16. this pin is also used with fs and psi# pins for phase dropping decoding. see table 1. vid7, vid6, vid5, vid4, vid3 , vid2, vid1 and vid0 - these are the inputs to the internal dac that generates the reference voltage for output regulation. all vid pins have no internal pull-up current sources until after td3. connect these pins either to open-drai n outputs with external pull-up resistors or to active-pull-up outputs, as high as vcc plus 0.3v. psi# - a low input signal indicates the low power mode operation of the processor. the controller drops the number of active phases to single or 2-phase operation, according to the logic on table 1 on page 14. the psi# pin, ss, and fs pins are used to program the controller in operation of non-coupled, 2-phase coupl ed, or (n-x)-phase coupled inductors when psi# is asserted (active low). different cases yield different pwm output behavior on both dropped phase(s) and remained phase(s) as psi# is asserted and de-asserted. a high input signal pulls the controller back to normal operation. operation multiphase power conversion microprocessor load current profiles have changed to the point that the advantages of multiphase power conversion are impossible to ignore. the technical challenges associated with producing a single-phase converter (which are both cost-effective and thermally viable), have forced a change to the cost-saving approach of multiphase. the isl6334, isl6334a controller helps reduce the complexity of implementation by integrating vital functions and requiring minimal output components. the block diagrams on pages page 5, 7, and 6 provide top level views of multiphase power conversion using the isl6334, isl6334a controller. interleaving the switching of each channel in a multiphase converter is timed to be symmetrically out-of-phase with each of the other channels. in a 3-phas e converter, each channel switches 1/3 cycle after the previous channel and 1/3 cycle before the following channel. as a result, the 3-phase converter has a combined ripple frequency 3x greater than the ripple frequency of any one phase. in addition, the peak-to-peak amplitude of the combined inductor currents is reduced in proportion to the number of phases (equations 1 and 2). increased ripple frequency and lower ripple amplitude mean that the desig ner can use less per-channel inductance and lower total output capacitance for any performance specification. figure 1 illustrates the multiplic ative effect on output ripple frequency. the three channel currents (il1, il2, and il3) combine to form the ac ripple current and the dc load current. the ripple component has 3x the ripple frequency of each individual channel current. each pwm pulse is terminated 1/3 of a cycle after the pwm pulse of the previous phase. the dc components of the inductor currents combine to feed the load. figure 1. pwm and inductor-current waveforms for 3-phase converter 1s/div pwm2, 5v/div pwm3, 5v/div il2, 7a/div il3, 7a/div il1 + il2 + il3, 7a/div il1, 7a/div pwm1, 5v/div isl6334, isl6334a
13 fn6482.1 may 28, 2009 to understand the reduction of ripple current amplitude in the multiphase circuit, examine e quation 1, which represents an individual channel?s peak-to-peak inductor current. in equation 1, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f sw is the switching frequency. the output capacitors conduct the ripple component of the inductor current. in the case of multiphase converters, the capacitor current is the sum of the ripple currents from each of the individual channels. compare equation 1 to the expression for the peak-to-peak current after the summation of n symmetrically phase-shi fted inductor currents in equation 2. peak-to-peak ripple current decreases by an amount proportional to the number of channels. output voltage ripple is a function of capacitance, capacitor equivalent series resistance (esr), and inductor ripple current. reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. another benefit of interleaving is to reduce input ripple current. input capacitance is determined in part by the maximum input ripple current. multiphase topologies can improve overall system cost and size by lo wering input ripple current and allowing the designer to reduce the cost of input capacitance. the example in figure 2 illustrates input currents from a three-phase converter combining to reduce the total input ripple current. the converter depicted in figure 2 delivers 36a to a 1.5v load from a 12v input. the rms input capacitor current is 5.9a. compare this to a single-phase converter also stepping down 12v to 1.5v at 36a. the single-phase converter has 11.9a rms input capacitor current. the single-phase converter must use an input capacitor bank with twice the rms current capacity as the equivalent three-phase converter. figures 18, 19 and 20 in the section entitled ?? on page 28 can be used to determine the input capacitor rms current based on load current, duty cycle, and the number of channels. they are provided as aids in determining the optimal input capacitor solution. figure 21 shows the single phase input-capacitor rms current for comparison. pwm modulation scheme the isl6334, isl6334a adopts intersil's proprietary active pulse positioning (app) mo dulation scheme to improve transient performance. app co ntrol is a un ique dual-edge pwm modulation scheme with both pwm leading and trailing edges being independently moved to give the best response to transient loads. the pwm frequency, however, is constant and set by the external resistor between the fs pin and gnd. to further improv e the transient response, the isl6334, isl6334a also implements intersil's proprietary adaptive phase alignment (apa) technique. apa, with sufficiently large load step currents, can turn on all phases together. with both app and apa control, isl6334, isl6334a can achieve excellent transient performance and reduce demand on the output capacitors. under steady state conditions, the operation of the isl6334, isl6334a pwm modulators appear to be that of a conventional trailing edge modulator. conventional analysis and design methods can therefore be used for steady state and small signal operation. pwm and psi# operation the timing of each channel is set by the number of active channels. the default channel setting for the isl6334, isl6334a is four. the switching cycle is defined as the time between pwm pulse termination signals of each channel. the cycle time of the pulse signal is the inverse of the switching frequency set by the resistor between the fs pin and ground. the pwm signals command the mosfet driver to turn on/off the channel mosfets. for 4-channel operation, the channel firing order is 1-2-3-4: pwm3 pulse happens 1/4 of a cycle after pwm4, pwm2 output follows a nother 1/4 of a cycle after pwm3, and pwm1 delays another 1/4 of a cycle after pwm2. for 3-channel operation, the chan nel firing order is 1-2-3. connecting pwm4 to vcc selects three channel operation and the pulse times are spaced in 1/3 cycle increments. if pwm3 is connected to vcc, two channel operation is selected and the pwm2 pulse happens 1/2 of a cycle after pwm1 pulse. if pwm2 is connected to vcc, only channel 1 operation is selected. in addition, tie psi# to gnd to configure for single or 2-phase operation with diode emulation on remaining channel(s), channel 1 or channels 1 and 3. i pp v in v out ? () v out lf sw v in ----------------------------------------------------- - = (eq. 1) figure 2. channel input currents and input- capacitor rms current for 3-phase converter channel 3 input current 10a/div channel 2 input current 10a/div channel 1 input current 10a/div input-capacitor current, 10a/div 1s/div i cpp , v in nv out ? () v out lf s v in ----------------------------------------------------------- - = (eq. 2) isl6334, isl6334a
14 fn6482.1 may 28, 2009 when psi# is asserted low, indicating the low power mode operation of the processor, the controller drops the number of active phases according to the logic on table 1 for highlight load efficiency performance. ss and fs pins are used to program the controller in ope ration of non-coupled, 2-phase coupled, or (n-x)-phase coupled inductors. different cases yield different pwm output behaviors on both dropped phase(s) and remained phase(s) as psi# is asserted and de-asserted. a high psi# input signal pulls the controller back to normal ccm pwm operation to sustain an immediate heavy transient load and high efficiency. note that ?n-x? means n-x phase coupled and x phase(s) are uncoupled. the dropped pwm is forced low for 200ns (uncoupled case) or until falling edge of coupled pwm (coupled case) then pulled to vcc/2, while the remained pwm(s) sends out a special 3-level pwm protocol that the dedicated vr11.1 drivers can decode and then enter diode emulation mode with gate drive volt age optimization. the isl6334a only generates 2-level normal ccm pwm except for faults. no dedicate d vr11.1 driver is required. see ?controller and driver recommendation? on page 3. while the controller is operational (vcc above por, en_vtt and en_pwr are both high, valid vid inputs), it can pull the pwm pins to ~40% of vcc (~2v for 5v vcc bias) during various stages, such as soft start delay, phase shedding operation, or fault conditions (oc or ov events). the matching driver's internal pwm resistor divider can further raise the pwm potential, but not lower it below the level set by the controller ic. therefore, the controller's pwm outputs are directly compat ible with intersil drivers that require 5v pwm signal ampl itudes. drivers requiring 3.3v pwm signal amplitudes are generally incompatible. switching frequency switching frequency is determined by the selection of the frequency-setting resistor, r t , which is connected from fs pin to gnd or vcc. equation 3 and figure 3 are provided to assist in selecting the correct resistor value. where f sw is the switching frequency of each phase. current sensing the isl6334, isl6334a senses cu rrent continuously for fast response. the isl6334, isl6334a supports inductor dcr sensing, or resistive sensi ng techniques. the associated channel current sense amplifier uses the isen inputs to reproduce a signal proportional to the inductor current, i l . the sense current, i sen , is proportional to the inductor current. the sensed current is used for current balance, load-line regulation, and overcurrent protection. the internal circuitry, shown in figures 4, and 5, represents one channel of an n-channel converter. this circuitry is repeated for each channel in the converter, but may not be active depending on the status of the pwm2, pwm3 and pwm4 pins, as described in ?pwm and psi# operation? on page 13. the input bias current of the current sensing amplifier is typically 60na; less than 5k input impedance is preferred to minimized the offset error. inductor dcr sensing an inductor?s winding is characteristic of a distributed resistance, as measured by the dcr (direct current resistance) parameter. consider the inductor dcr as a separate lumped quantity, as shown in figure 4. the channel current i l , flowing through the inductor, will also pass through the dcr. equation 4 shows the s-domain equivalent voltage across the inductor v l . a simple r-c network across th e inductor extracts the dcr voltage, as shown in figure 4. table 1. psi# operation decoding psi# fs ss non ci or (n-1) ci drops to 1-phase 0 0 0 non ci or (n-2) ci drops to 2-phase 0 0 1 2-phase ci drops to 1-phase 0 1 0 2-phase ci drops to 2-phase 0 1 1 normal ccm pwm mode 1 x x (eq. 3) r t 2.5x10 10 f sw ------------------------- - = figure 3. switching frequency vs rt frequency-setting resistor value (r t ) 250 200 150 100 50 0 100k 200k 300k 400k 500k 600k 700k 800k 900k 1m switching frequency (hz) v l s () i l sl dcr + ? () ? = (eq. 4) isl6334, isl6334a
15 fn6482.1 may 28, 2009 the voltage on the capacitor v c , can be shown to be proportional to the channel current i l . see equation 5. if the r-c network components are selected such that the rc time constant (= r*c) matches the inductor time constant (= l/dcr), the voltage across the capacitor v c is equal to the voltage drop across the dcr, i.e., proportional to the channel current. with the internal low-offset cu rrent amplifier, the capacitor voltage v c is replicated across the sense resistor r isen . therefore, the current out of isen+ pin, i sen , is proportional to the inductor current. because of the internal filter at isen- pin, one capacitor, c t , is needed to match the time delay between the isen- and isen+ signals. select the proper c t to keep the time constant of r isen and c t (r isen x c t ) close to 27ns. equation 6 shows that the ratio of the channel current to the sensed current, i sen , is driven by the value of the sense resistor and the dcr of the inductor. resistive sensing for accurate current sense, a de dicated current-sense resistor r sense in series with each output inductor can serve as the current sense element (see figure 5). this technique is more accurate, but reduces overall converter efficiency due to the additional power loss on the current sense element r sense . the same capacitor c t is needed to match the time delay between isen- and isen+ signals. select the proper c t to keep the time constant of r isen and c t (r isen x c t ) close to 27ns. equation 7 shows the ratio of the channel current to the sensed current i sen . the inductor dcr value will in crease as the temperature increases. therefore, the sens ed current will increase as the temperature of the current sens e element increases. in order to compensate the temperature effect on the sensed current signal, a positive temperature coefficient (ptc) resistor can be selected for the sense resistor r isen , or the integrated temperature compensation func tion of isl6334, isl6334a should be utilized. the integrat ed temperature compensation function is described in ?exter nal temperature compensation? on page 24. channel-current balance the sensed current i n from each active channel is summed together and divided by the num ber of active channels. the resulting average current i avg provides a measure of the total load current. channel current balance is achieved by comparing the sensed current of each channel to the average current to make an appropriate adjustment to the pwm duty cycle of each channel with intersil?s patented current-balance method. channel current balance is essential in achieving the thermal advantage of multiphase operation. with good current balance, the power loss is equally dissipated over multiple devices and a greater area. figure 4. dcr sensing configuration i n i sen i l dcr r isen ----------------- - = - + isen-(n) current sense v in isen+(n) pwm(n) isl6596 r isen(n) dcr l inductor r v out c out - + v c (s) c i l s () - + v l c t isl6334, isl6334a internal circuit v c s () s l dcr ------------- ? 1 + ?? ?? dcr i l ? () ? src 1 + ? () -------------------------------------------------------------------- - = (eq. 5) i sen i l dcr r isen ----------------- - ? = (eq. 6) i sen i l r sense r isen ----------------------- ? = (eq. 7) figure 5. sense resistor in series with inductors i n i sen i l r sense r isen -------------------------- = - + isen-(n) current sense isen+(n) r isen(n) r sense l v out c out i l c t isl6334, isl6334a internal circuit isl6334, isl6334a
16 fn6482.1 may 28, 2009 voltage regulation the compensation network shown in figure 6 assures that the steady-state error in the output voltage is limited only to the error in the reference vo ltage (output of the dac) and offset errors in the ofs current source, remote-sense and error amplifiers. intersil specifies the guaranteed tolerance of the isl6334, isl6334a to include the combined tolerances of each of these elements. the sensed average current i avg is tied to fb internally. this current will develop voltage drop across the resistor between fb and vdiff pins for droop control. isl6334, isl6334a can not be used for non-droop applications. the output of the error amplifier, v comp , is compared to sawtooth waveforms to generate the pwm signals. the pwm signals control the timing of the intersil mosfet drivers and regulate the converter output to the specified reference voltage. the internal and external circuitry, which control voltage regulation, are illustrated in figure 6 . the isl6334, isl6334a incorporates an internal differential remote-sense amplifier in the feedback path. the amplifier removes the voltage error encountered when measuring the output voltage relative to the local controller ground reference point, resulting in a more accurate means of sensing output voltage. connect the microprocessor sense pins to the non-inverting input, vsen, and inverting input, rgnd, of the remote-sense amplifier. the remote-sense output, v diff , is connected to the inverting input of the error amplifier through an external resistor. a digital-to-analog converter (dac) generates a reference voltage based on the state of logic signals at pins vid7 through vid0. the dac decodes the eight 6-bit logic signal (vid) into one of the discrete voltages shown in table 2. all vid pins have no internal pull-up current sources after t d3 . after t d3 , each vid input offers a minimum 30a pull-up to an internal 2.5v source for use with open-drain outputs. the pull-up current diminishes to zero above the logic threshold to protect voltage-sensitive outp ut devices. external pull-up resistors can augment the pull- up current sources in case leakage into the driving device is greater than 30a. figure 6. output voltage and load-line regulation with offset adjustment i avg external circuit isl6334, isl6334a internal circui t comp r c r fb fb vdiff vsen rgnd - + v droop error amplifier - + v out + differential remote-sense amplifier v comp c c ref dac r ref c ref - + v out - table 2. vr11 vid 8 bit vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 00000000 off 00000001 off 000000101. 60000 000000111. 59375 000001001. 58750 000001011. 58125 000001101. 57500 000001111. 56875 000010001. 56250 000010011. 55625 000010101. 55000 000010111. 54375 000011001. 53750 000011011. 53125 000011101. 52500 000011111. 51875 000100001. 51250 000100011. 50625 000100101. 50000 000100111. 49375 000101001. 48750 000101011. 48125 000101101. 47500 000101111. 46875 000110001. 46250 000110011. 45625 000110101. 45000 000110111. 44375 000111001. 43750 000111011. 43125 000111101. 42500 000111111. 41875 001000001. 41250 isl6334, isl6334a
17 fn6482.1 may 28, 2009 0 0 1 0 0 0 0 1 1.40625 0 0 1 0 0 0 1 0 1.40000 0 0 1 0 0 0 1 1 1.39375 0 0 1 0 0 1 0 0 1.38750 0 0 1 0 0 1 0 1 1.38125 0 0 1 0 0 1 1 0 1.37500 0 0 1 0 0 1 1 1 1.36875 0 0 1 0 1 0 0 0 1.36250 0 0 1 0 1 0 0 1 1.35625 0 0 1 0 1 0 1 0 1.35000 0 0 1 0 1 0 1 1 1.34375 0 0 1 0 1 1 0 0 1.33750 0 0 1 0 1 1 0 1 1.33125 0 0 1 0 1 1 1 0 1.32500 0 0 1 0 1 1 1 1 1.31875 0 0 1 1 0 0 0 0 1.31250 0 0 1 1 0 0 0 1 1.30625 0 0 1 1 0 0 1 0 1.30000 0 0 1 1 0 0 1 1 1.29375 0 0 1 1 0 1 0 0 1.28750 0 0 1 1 0 1 0 1 1.28125 0 0 1 1 0 1 1 0 1.27500 0 0 1 1 0 1 1 1 1.26875 0 0 1 1 1 0 0 0 1.26250 0 0 1 1 1 0 0 1 1.25625 0 0 1 1 1 0 1 0 1.25000 0 0 1 1 1 0 1 1 1.24375 0 0 1 1 1 1 0 0 1.23750 0 0 1 1 1 1 0 1 1.23125 0 0 1 1 1 1 1 0 1.22500 0 0 1 1 1 1 1 1 1.21875 0 1 0 0 0 0 0 0 1.21250 0 1 0 0 0 0 0 1 1.20625 0 1 0 0 0 0 1 0 1.20000 0 1 0 0 0 0 1 1 1.19375 0 1 0 0 0 1 0 0 1.18750 0 1 0 0 0 1 0 1 1.18125 0 1 0 0 0 1 1 0 1.17500 0 1 0 0 0 1 1 1 1.16875 0 1 0 0 1 0 0 0 1.16250 table 2. vr11 vid 8 bit (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 010010011. 15625 010010101. 15000 010010111. 14375 010011001. 13750 010011011. 13125 010011101. 12500 010011111.11875 010100001.11250 010100011. 10625 010100101. 10000 010100111. 09375 010101001. 08750 010101011. 08125 010101101. 07500 010101111. 06875 010110001. 06250 010110011. 05625 010110101. 05000 010110111. 04375 010111001. 03750 010111011. 03125 010111101. 02500 010111111. 01875 011000001. 01250 011000011. 00625 011000101. 00000 011000110. 99375 011001000. 98750 011001010. 98125 011001100. 97500 011001110. 96875 011010000. 96250 011010010. 95625 011010100. 95000 011010110. 94375 011011000. 93750 011011010. 93125 011011100. 92500 011011110. 91875 011100000. 91250 table 2. vr11 vid 8 bit (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage isl6334, isl6334a
18 fn6482.1 may 28, 2009 load-line regulation some microprocessor manufacturers require a precisely controlled output resistance. this dependence of output voltage on load current is often termed ?droop? or ?load line? regulation. by adding a well controlled output impedance, the output voltage can effectively be level shifted in a direction, which works to ac hieve the load-line regulation required by these manufacturers. in other cases, the designer may determine that a more cost-effective solution can be achieved by adding droop. droop can help to reduce the output-voltage spike that results from fast load-current demand changes. the magnitude of the spike is dictated by the esr and esl of the output capacitors select ed. by positioning the no-load 0 1 1 1 0 0 0 1 0.90625 0 1 1 1 0 0 1 0 0.90000 0 1 1 1 0 0 1 1 0.89375 0 1 1 1 0 1 0 0 0.88750 0 1 1 1 0 1 0 1 0.88125 0 1 1 1 0 1 1 0 0.87500 0 1 1 1 0 1 1 1 0.86875 0 1 1 1 1 0 0 0 0.86250 0 1 1 1 1 0 0 1 0.85625 0 1 1 1 1 0 1 0 0.85000 0 1 1 1 1 0 1 1 0.84375 0 1 1 1 1 1 0 0 0.83750 0 1 1 1 1 1 0 1 0.83125 0 1 1 1 1 1 1 0 0.82500 0 1 1 1 1 1 1 1 0.81875 1 0 0 0 0 0 0 0 0.81250 1 0 0 0 0 0 0 1 0.80625 1 0 0 0 0 0 1 0 0.80000 1 0 0 0 0 0 1 1 0.79375 1 0 0 0 0 1 0 0 0.78750 1 0 0 0 0 1 0 1 0.78125 1 0 0 0 0 1 1 0 0.77500 1 0 0 0 0 1 1 1 0.76875 1 0 0 0 1 0 0 0 0.76250 1 0 0 0 1 0 0 1 0.75625 1 0 0 0 1 0 1 0 0.75000 1 0 0 0 1 0 1 1 0.74375 1 0 0 0 1 1 0 0 0.73750 1 0 0 0 1 1 0 1 0.73125 1 0 0 0 1 1 1 0 0.72500 1 0 0 0 1 1 1 1 0.71875 1 0 0 1 0 0 0 0 0.71250 1 0 0 1 0 0 0 1 0.70625 1 0 0 1 0 0 1 0 0.70000 1 0 0 1 0 0 1 1 0.69375 1 0 0 1 0 1 0 0 0.68750 1 0 0 1 0 1 0 1 0.68125 1 0 0 1 0 1 1 0 0.67500 1 0 0 1 0 1 1 1 0.66875 1 0 0 1 1 0 0 0 0.66250 table 2. vr11 vid 8 bit (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 100110010. 65625 100110100. 65000 100110110. 64375 100111000. 63750 100111010. 63125 100111100. 62500 100111110. 61875 101000000. 61250 101000010. 60625 101000100. 60000 101000110. 59375 101001000. 58750 101001010. 58125 101001100. 57500 101001110. 56875 101010000. 56250 101010010. 55625 101010100. 55000 101010110. 54375 101011000. 53750 101011010. 53125 101011100. 52500 101011110. 51875 101100000. 51250 101100010. 50625 101100100. 50000 11111110 off 11111111 off table 2. vr11 vid 8 bit (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage isl6334, isl6334a
19 fn6482.1 may 28, 2009 voltage level near the upper s pecification limit, a larger negative spike can be sustained without crossing the lower limit. by adding a well cont rolled output impedance, the output voltage under load can effectively be level shifted down so that a larger positive spike can be sustained without crossing the upper specification limit. as shown in figure 6, a current proportional to the average current of all active channels, i avg , flows from fb through a load-line regulation resistor r fb . the resulting voltage drop across r fb is proportional to the output current, effectively creating an output voltage droo p with a steady-state value defined as shown in equation 8: the regulated output voltage is reduced by the droop voltage v droop . the output voltage as a func tion of load current is derived by combining equat ion 8 with the appropriate sample current expression defined by the current sense method employed, as shown in equation 9: where v ref is the reference voltage, v ofs is the programmed offset voltage, i load is the total output current of the converter, r isen is the sense resistor connected to the isen+ pin, and r fb is the feedback resistor, n is the active channel number, and r x is the dcr, or r sense depending on the sensing method. therefore, the equivalent lo adline impedance, i.e. droop impedance, is equal to equation 10: output-voltage offset programming the isl6334, isl6334a allows the designer to accurately adjust the offset voltage. when a resistor, r ofs , is connected between ofs to vcc, the voltage across it is regulated to 1.6v. this causes a proportional current (i ofs ) to flow into ofs. if r ofs is connected to ground, the voltage across it is regulated to 0.4v, and i ofs flows out of ofs. a resistor between dac and ref, r ref , is selected so that the product (i ofs x r ofs ) is equal to the desired offset voltage. these functions are shown in figure 7. once the desired output offset voltage has been determined, use equations 11 and 12 to calculate r ofs : for positive offset (connect r ofs to vcc): for negative offset (connect r ofs to gnd): dynamic vid modern microprocessors need to make changes to their core voltage as part of normal operation. they direct the core- voltage regulator to do this by making changes to the vid inputs during regulator operation. the power management solution is required to monitor the dac inputs and respond to on-the-fly vid changes in a co ntrolled manner. supervising the safe output voltage transition within the dac range of the processor without discontinuity or disruption is a necessary function of the core-voltage regulator. in order to ensure the smooth transition of output voltage during vid change, a vid step change smoothing network, composed of r ref and c ref , as shown in figure 7, can be used. the selection of r ref is based on the desired offset voltage as detailed in ?output-voltage offset programming? on page 19. the selection of c ref is based on the time duration for 1-bit vid change and the allowable delay time. assuming the microprocessor controls the vid change at 1-bit every t vid , the relationship between the time constant of r ref and c ref network and t vid is given by equation 13. during dynamic vid transition and vid steps up, the overcurrent trip point increases by 140% to avoid falsely triggering ocp circuits, while the overvoltage trip point is set to its maximum vid ovp trip le vel. if the dynamic vid occurs at psi# asserted, the system s hould exit psi# and complete the transition, and then resume psi# operation 50s after the transition. v droop i avg r fb = (eq. 8) v out v ref v ofs ? i load n ---------------- - r x r isen ----------------- -r fb ?? ?? ?? ? = (eq. 9) r ll r fb n ------------ r x r isen ----------------- - = (eq. 10) r ofs 1.6 r ref v offset ------------------------------ = (eq. 11) r ofs 0.4 r ref v offset ----------------------------- - = (eq. 12) dynamic vid d/a e/a vcc dac fb ref ofs vcc gnd + - + - 0.4v 1.6v or gnd r ofs r ref isl6334, isl6334a figure 7. output volt age offset programming c ref c ref r ref t vid = (eq. 13) isl6334, isl6334a
20 fn6482.1 may 28, 2009 operation initialization prior to converter initialization, proper conditions must exist on the enable inputs and vcc. when the conditions are met, the controller begins soft-sta rt. once the output voltage is within the proper window of operation, vr_rdy asserts logic high. enable and disable while in shutdown mode, the pwm outputs are held in a high-impedance state to assure the drivers remain off. the following input conditions must be met before the isl6334, isl6334a is released from shutdown mode. 1. the bias voltage applied at vcc must reach the internal power-on reset (por) rising threshold. once this threshold is reached, proper operation of all aspects of the isl6334, isl6334a are guaranteed. hysteresis between the rising and falling thresholds assure that once enabled, isl6334, isl6334a will not inadvertently turn off unless the bias voltage drops substantially (see ?electrical specifications ? table beginning on page 8). 2. the isl6334, isl6334a features an enable input (en_pwr) for power sequencing between the controller bias voltage and another voltage rail. the enable comparator holds the isl6334, isl6334a in shutdown until the voltage at en_pwr rises above 0.875v. the enable comparator has about 130mv of hysteresis to prevent bounce. it is important that the driver reach their por level before the isl 6334, isl6334a becomes enabled. the schematic in figure 8 demonstrates sequencing the isl6334, isl6334a with the isl66xx family of intersil mosfet drivers, which require 12v bias. 3. the voltage on en_vtt must be higher than 0.875v to enable the controller. this pin is typically connected to the output of vtt vr. when all conditions previously mentioned are satisfied, isl6334, isl6334a begins the soft-start and ramps the output voltage to 1.1v first. after remaining at 1.1v for some time, isl6334, isl6334a reads the vid code at vid input pins. if the vid code is valid, isl6334, isl6334a will regulate the output to the final vid setting. if the vid code is off code, isl6334, isl6334a will shut down, and cycling vcc, en_pwr or en_vtt is needed to restart. soft-start isl6334, isl6334a based vr has 4 periods during soft-start, as shown in figure 9. after vcc, en_vtt and en_pwr reach their por/enable thresholds, the controller will have a fixed delay period t d1 . after this delay period, the vr will begin first soft-start ramp until the ou tput voltage reaches 1.1v v boot voltage. then, the controller will r egulate the vr voltage at 1.1v for another fixed period t d3 . at the end of t d3 period, isl6334, isl6334a reads the vid signals. if the vid code is valid, isl6334, isl6334a will initiate the second soft-start ramp until the voltage reaches the vid voltage minus offset voltage. the soft-start time is the sum of the 4 periods as shown in equation 14. t d1 is a fixed delay with the typical value as 1.36ms. t d3 is determined by the fixed 85s plus the time to obtain valid vid voltage. if the vid is valid before the output reaches the 1.1v, the minimum time to validate the vid input is 500ns. therefore, the minimum t d3 is about 86s. during t d2 and t d4 , isl6334, isl6334a digitally controls the dac voltage change at 6.25mv per step. the time for each step is determined by the frequency of the soft-start oscillator, which is defined by the resistor r ss from ss pin to gnd. the second soft-start ramp time t d2 and t d4 can be calculated based on equations 15 and 16: for example, when vid is set to 1.5v and the r ss is set at 100k , the first soft-start ramp time t d2 will be 704s and the second soft-start ramp time t d4 will be 256s. after the dac voltage reaches the final vid setting, vr_rdy will be set to high with the fixed delay t d5 . the typical value for t d5 is 85s. before the vr_rdy is released, the controller di sregards the psi# input and always operates in normal ccm pwm mode. figure 8. power sequencing using threshold- sensitive enable (en) function - + 0.875v external circuit isl6334, isl6334a internal circuit en_pwr +12v por circuit 100k 9.1k enable comparator soft-start and fault logic en_vtt vcc + - 0.875v t ss t d1 t d2 t d3 t d4 +++ = (eq. 14) t d2 1.1xr ss 6.25x25 ----------------------- - s () = (eq. 15) t d4 v vid 1.1 ? () xr ss 6.25x25 ------------------------------------------------ s () = (eq. 16) isl6334, isl6334a
21 fn6482.1 may 28, 2009 current sense output the current flowing out of the imon pin is equal to the sensed average current inside isl6334, isl6334a. in typical applications, a resistor is plac ed from the imon pin to gnd to generate a voltage, which is proportional to the load current and the resistor value, as shown in equation 17: where v imon is the voltage at the imon pin, r imon is the resistor between the imon pin and gnd, i load is the total output current of the converter, r isen is the sense resistor connected to the isen+ pin, n is the active channel number, and r x is the dc resistance of the current sense element, either the dcr of the inductor or r sense depending on the sensing method. the resistor from the imon pin to gnd should be chosen to ensure that the voltage at the imon pin is less than 1.11v under the maximum load current. if the imon pin voltage is higher than 1.11v, overcurrent shutdown will be triggered, as described in ?overcurrent protection? on page 22. a small capacitor can be placed between the imon pin and gnd to reduce the noise impact. if this pin is not used, tie it to gnd. fault monitoring and protection the isl6334, isl6334a actively monitors output voltage and current to detect fault conditions. fault monitors trigger protective measures to prevent damage to a microprocessor load. one common power-good indicator is provided for linking to external system monitors. the schematic in figure 10 outlines the interaction between the fault monitors and the vr_rdy signal. vr_rdy signal the vr_rdy pin is an open-drain logic output which indicates that the soft-start period has completed and the output voltage is within the regulated range. vr_rdy is pulled low during shutdown and releases high after a successful soft-start and a fixed delay t d5 . vr_rdy will be pulled low when an undervoltage or overvoltage condition is detected, or the controller is disabled by a reset from en_pwr, en_vtt, por, or vid off-code. undervoltage detection the undervoltage threshold is set at 50% of the vid code. when the output voltage at vsen is below the undervoltage threshold, vr_rdy is pulled low. overvoltage protection regardless of the vr being enabled or not, the isl6334, isl6334a overvoltage protection (ovp) circuit will be active after its por. the ovp thresholds are different under different operation conditions. when vr is not enabled and during the soft-start intervals t d1 , t d2 and t d3 , the ovp threshold is 1.273v. once the controller detects valid vid input, the ovp trip point will be changed to dac plus 175mv. two actions are taken by isl6334, isl6334a to protect the microprocessor load when an overvoltage condition occurs. at the inception of an overvolt age event, all pwm outputs are commanded low instantly (less than 20ns). this causes the intersil drivers to turn on the lower mosfets and pull the output voltage below a level to avoid damaging the load. when the vdiff voltage falls below the dac plus 75mv, pwm signals enter a high-impedance state. the intersil drivers respond to the high-impedance input by turning off both upper and lower mosfets. if the overvoltage condition reoccurs, isl6334, isl6334a will again command the lower mosfets to turn on. isl6334, isl6334a will c ontinue to protect the load in this fashion as long as the overvoltage condition occurs. once an overvoltage condition is detected, normal pwm operation ceases until isl6334 , isl6334a is reset. cycling the voltage on en_pwr, en_vtt or vcc below the por-falling threshold will reset the controller. cycling the vid codes will not reset the controller.. figure 9. soft-start waveforms vout, 500mv/div en_vtt 500s/div t d3 t d4 t d5 vr_rdy t d1 t d2 v iout r iout n ------------------- r x r isen ----------------- -i load = (eq. 17) figure 10. vr_rdy and protection circuitry - + vid + 0.175v vdiff - + 105a i avg - + dac ov oc uv vr_rdy 50% soft-start, fault and control logic - + oc imon 1.11v isl6334, isl6334a
22 fn6482.1 may 28, 2009 overcurrent protection isl6334, isl6334a has two levels of overcurrent protection. each phase is protected from a sustained overcurrent condition by limiting its peak current, while the combined phase currents are protected on an instantaneous basis. in instantaneous protecti on mode, isl6334, isl6334a utilizes the sensed average current i avg to detect an overcurrent condition. see ?c hannel-current balance? on page 15 for more details on how the average current is measured. the average current is continually compared with a constant 105a reference curr ent, as shown in figure 10. once the average current exceeds the reference current, a comparator triggers the converter to shutdown. the current out of imon pin is equal to the sensed average current i avg . with a resistor from imon to gnd, the voltage at imon will be proportional to the sensed average current and the resistor value. the isl6334, isl6334a continuously monitors the voltage at imon pin. if the voltage at imon pin is higher than 1.11v, a comp arator triggers the overcurrent shutdown. by increasing the resistor between imon and gnd, the overcurrent protection threshold can be adjusted to be less than 105a. for example, the overcurrent threshold for the sensed average current i avg can be set to 95a by using a 11.8k resistor from imon to gnd. at the beginning of overcurrent shutdown, the controller places all pwm signals in a high-impedance state within 20ns, commanding the intersil mosfet driver ics to turn off both upper and lower mosfets. the system remains in this state a period of 4096 switching cycles. if the controller is still enabled at the end of this wait period, it will attempt a soft-start. if the fault remain s, the trip-retry cycles will continue indefinitely (as shown in figure 11) until either controller is disabled or the fa ult is cleared. note that the energy delivered during trip-retry cycling is much less than during full-load operation, so there is no thermal hazard during this kind of operation. for the individual channel ov ercurrent protection, isl6334, isl6334a continuously compares the sensed current signal of each channel with the 129a reference current. if one channel current exceeds the reference current, isl6334, isl6334a will pull pwm signal of this channel to low for the rest of the switching cycle. th is pwm signal can be turned on next cycle if the sensed c hannel current is less than the 129a reference current. the peak current limit of individual channel will not trigger the converter to shutdown. thermal monitoring (vr_hot/vr_fan) there are two thermal signals to indicate the temperature status of the voltage regulator: vr_hot and vr_fan. both vr_fan and vr_hot pins are open-drain outputs, and external pull-up resistors are required. those signals are valid only after the controller is enabled. the vr_fan signal indicates that the temperature of the voltage regulator is high and more cooling airflow is needed. the vr_hot signal can be used to inform the system that the temperature of the voltage regulator is too high and the cpu should reduce its power consumption. the vr_hot signal may be tied to the cpu?s proc_hot signal. the diagram of thermal monitoring function block is shown in figure 12. one ntc resistor should be placed close to the power stage of the voltage regulator to sense the operational temperature, and one pull-up resistor is needed to form the voltage divider for the tm pin. as the temperatur e of the power stage increases, the resistance of the ntc will reduce, resulting in the reduced voltage at the tm pin. figure 13 shows the tm voltage over the temperature for a typical design with a recommended 6.8k ntc (p/n: nths0805n02n6801 from vishay) and 1k resistor rtm1. we recommend using those resistors for the accurate temperature compensation. there are two comparators with hysteresis to compare the tm pin voltage to the fixed thresholds for vr_fan and vr_hot signals respectively. the vr_fan signal is set to high when the tm voltage is lower than 39.1% of vcc voltage, and is pulled to gnd when the tm voltage increases to above 45.1% of vcc voltage. the vr_fan signal is set to high when the tm voltage goes below 33.3% of vcc voltage, and is pulled to gnd when the tm voltage goes back to above 39.1% of vcc voltage. figure 14 shows the operation of those signals. 0a 0v 2ms/div output current figure 11. overcurrent behavior in hiccup mode. f sw = 500khz output voltage isl6334, isl6334a
23 fn6482.1 may 28, 2009 based on the ntc temperatur e characteristics and the desired threshold of the vr_hot signal, the pull-up resistor rtm1 of tm pin is given by equation 18: r ntc(t3) is the ntc resistance at the vr_hot threshold temperature t3. the ntc resistance at the set point t2 and release point t1 of vr_fan signal can be calculated as shown in equations 19 and 20: with the ntc resistance valu e obtained from equations 19 and 20, the temperature value t2 and t1 can be found from the ntc datasheet. temperature compensation the isl6334, isl6334a supports inductor dcr sensing, or resistive sensing techniques. the inductor dcr has a positive temperature coefficient, which is about +0.385%/c. since the voltage across induct or is sensed for the output current information, the sensed current has the same positive temperature coefficient as the inductor dcr. in order to obtain the correct current information, there should be a way to correct t he temperature impact on the current sense component. isl6334, isl6334a provides two methods: integrated temperat ure compensation and external temperature compensation. integrated temperature compensation when the tcomp voltage is equa l or greater than vcc/15, isl6334, isl6334a will utilize the voltage at tm and tcomp pins to compensate t he temperature impact on the sensed current. the block diagram of this function is shown in figure 15.. when the tm ntc is placed close to the current sense component (inductor), the temperature of the ntc will track the temperature of the curren t sense component. therefore the tm voltage can be utilized to obtain the temperature of the current sense component. figure 12. block diagram of thermal monitoring function 0.333v cc 0.391v cc o c r tm1 r ntc vcc tm vr_fan vr_hot figure 13. the ratio of tm voltage to ntc temperature with recommended parts 20 30 40 50 60 70 80 90 100 0 20 40 60 80 100 120 140 temperature (c) v tm /v cc (%) tm vr_fan vr_hot 0.451*vcc 0.391*vcc 0.333*vcc temperature t1 t2 t3 figure 14. vr_hot and vr_fan signal vs tm voltage r tm1 2.75xr ntc t3 () = (eq. 18) r ntc t2 () 1 . 267 x r ntc t3 () = (eq. 19) r ntc t1 () 1.644xr ntc t3 () = (eq. 20) figure 15. block diagram of integrated temperature compensation o c r tm1 r ntc tm r tc1 r tc2 tcomp v cc non-linear a/d 4-bit a/d droop and overcurrent protection i 1 i 2 i 3 i 4 k i d/a channel current sense i sen4 i sen3 i sen2 i sen1 v cc isl6334, isl6334a
24 fn6482.1 may 28, 2009 based on vcc voltage, isl6334, isl6334a converts the tm pin voltage to a 6-bit tm digital signal for temperature compensation. with the non-linear a/d converter of isl6334, isl6334a, the tm digital signal is linearly proportional to the ntc temperature. for accurate temperature compensation, the ra tio of the tm voltage to the ntc temperature of the practical design should be similar to that in figure 13. depending on the location of the ntc and the airflow, the ntc may be cooler or hotter than the current sense component. the tcomp pin voltage can be utilized to correct the temperature difference between ntc and the current sense component. when a different ntc type or different voltage divider is used for the tm function, the tcomp voltage can also be used to compensate for the difference between the recommended tm voltage curve in figure 14 and that of the actu al design. according to the vcc voltage, isl6334, isl6334a converts the tcomp pin voltage to a 4-bit tcomp digital signal as tcomp factor n. the tcomp factor n is an integer between 0 and 15. the integrated temperature compensation function is disabled for n = 0. for n = 4, the ntc temperature is equal to the temperature of the current s ense component. for n < 4, the ntc is hotter than the current sense component. the ntc is cooler than the current sense component for n > 4. when n > 4, the larger tcomp factor n, the larger the difference between the ntc temperature and the temperature of the current sense component. isl6334, isl6334a multiplexes the tcomp factor n with the tm digital signal to obtain the adjustment gain to compensate the temperature impact on the sensed channel current. the compensated channel current signal is used for droop and overcurrent protection functions. design procedure 1. properly choose the voltage divider for the tm pin to match the tm voltage vs temperature curve with the recommended curve in figure 13. 2. run the actual board under th e full load and the desired cooling condition. 3. after the board reaches the th ermal steady state, record the temperature (t csc ) of the current sense component (inductor or mosfet) and the voltage at tm and vcc pins. 4. use equation 21 to calculate the resistance of the tm ntc, and find out the corresponding ntc temperature t ntc from the ntc datasheet. 5. use equation 22 to calculate the tcomp factor n: 6. choose an integral number close to the above result for the tcomp factor. if this factor is higher than 15, use n = 15. if it is less than 1, use n = 1. 7. choose the pull-up resistor r tc1 (typical 10k ); 8. if n = 15, one does not need the pull-down resistor r tc2 . if otherwise, obtain r tc2 using equation 23: 9. run the actual board under full load again with the proper resistors connected to the tcomp pin. 10. record the output voltage as v1 immediately after the output voltage is stable with the full load. record the output voltage as v2 after the vr reaches the thermal steady state. 11. if the output voltage in creases over 2mv as the temperature increases, i.e. v2 - v1 > 2mv, reduce n and redesign r tc2 ; if the output voltage decreases over 2mv as the temperature increase s, i.e. v1 - v2 > 2mv, increase n and redesign r tc2 . external temperature compensation by pulling the tcomp pin to gnd, the integrated temperature compensation function is disabled. in addition, one external temperature compensation network, shown in figure 16, can be used to cancel the temperatur e impact on the droop (i.e., load line). the sensed current will flow out of the fb pin and develop a droop voltage across the resistor equivalent (r fb ) between the fb and vdiff pins. if r fb resistance reduces as the temperature increases, the te mperature impact on the droop can be compensated. an ntc resistor can be placed close to the power stage and used to form r fb . due to the non-linear temperature characteristics of t he ntc, a resistor network is needed to make the equivalent resistance between the fb and vdiff pins reverse proportional to the temperature. the external temperature co mpensation network can only compensate the temperature impa ct on the droop, while it has no impact to the sensed current inside isl6334, isl6334a. therefore, this network ca nnot compensate for the temperature impact on the ov ercurrent protection function. r ntc t ntc () v tm xr tm1 v cc v ? tm ------------------------------- - = (eq. 21) n 209x t csc t ? ntc () 3xt ntc 400 + ------------------------------------------------------- - 4 + = (eq. 22) r tc2 nxr tc1 15 n ? ----------------------- = (eq. 23) figure 16. external temperature compensation fb vdiff o c isen comp isl6334, isl6334a internal circuit isl6334, isl6334a
25 fn6482.1 may 28, 2009 general design guide this design guide is intended to provide a high-level explanation of the steps neces sary to create a multiphase power converter. it is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following. in addition to this guide, intersil provides complete reference designs, which include schematics, bills of materials, and example board layouts for all common microprocessor applications. power stages the first step in designing a multiphase converter is to determine the number of phases. this determination depends heavily upon the cost analysis, which in turn depends on system constraints that differ from one design to the next. principally, the designer will be concerned with whether components can be mounted on both sides of the circuit board; whether through-hole components are permitted; and the total board space available for power supply circuitry. generally speaking, the most economical solutions are those in which each phase handles between 15a and 25a. all surface-mount designs will tend toward the lower end of this current range. if through-hole mosfets and inductors can be used, higher per-phase currents are possible. in cases where board space is the limiting constraint, current can be pushed as high as 40a per phase, but these designs require heat sinks and forced air to cool the mosfets, inductors and heat-dissipating surfaces. mosfets the choice of mosfets depends on the current each mosfet will be required to conduct; the switching frequency; the capability of the mosfets to dissipate heat; and the availability and nature of heat sinking and air flow. lower mosfet power calculation the calculation for heat dissipated in the lower mosfet is simple, since virtually all of the heat loss in the lower mosfet is due to current conducted through the channel resistance (r ds(on) ). in equation 24, i m is the maximum continuous output current; i pp is the peak-to-peak inductor current (see equation 1); d is the duty cycle (v out /v in ); and l is the per-channel inductance. an additional term can be added to the lower-mosfet loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower-mosfet body diode. this term is dependent on the diode forward voltage at i m , v d(on) ; the switching frequency, f sw ; and the length of dead times, t d1 and t d2 , at the beginning and the end of the lower-mosfet conduction interval respectively. thus the total maximum power dissipated in each lower mosfet is approximated by the summation of p low,1 and p low,2 . upper mosfet power calculation in addition to r ds(on) losses, a large portion of the upper- mosfet losses are due to currents conducted across the input voltage (v in ) during switching. since a substantially higher portion of the upper-mosfet losses are dependent on switching frequency, the power calculation is more complex. upper mosfet losses can be divided into separate components involving the upper-mosfet switching times; the lower-mosfet body-diode reverse-recovery charge, q rr ; and the upper mosfet r ds(on) conduction loss. when the upper mosfet turns of f, the lower mosfet does not conduct any portion of th e inductor current until the voltage at the phase node falls below ground. once the lower mosfet begins conducting, the current in the upper mosfet falls to zero as the current in the lower mosfet ramps up to assume the full inductor current. in equation 26, the required time for this commutation is t 1 and the approximated associated power loss is p up,1 .. at turn on, the upper mosfet begins to conduct and this transition occurs over a time t 2 . in equation 27, the approximate power loss is p up,2 . a third component involves the lower mosfet?s reverse-recovery charge, q rr . since the inductor current has fully commutated to the upper mosfet before the lower-mosfet?s body diode can draw all of q rr , it is conducted through the upper mosfet across vin. the power dissipated as a result is p up,3 and is approximated in equation 28: finally, the resistive part of t he upper mosfet?s is given in equation 29 as p up,4 . the total power dissipated by the upper mosfet at full load can now be approximated as the summation of the results from equations 26, 27, and 28. since the power equations depend on mosfet parameters, choosing the correct mosfets can be an iterative process involving repetitive solutions to the loss equations for different mosfets and different switching frequencies, as shown in equation 29. current sensing resistor the resistors connected to the isen+ pins determine the gains in the load-line regulation loop and the channel-current p low 1 , r ds on () i m n ----- - ?? ?? ?? 2 1d ? () i lp-p , 2 1d ? () 12 --------------------------------- - + = (eq. 24) p low 2 , v don () f sw i m n ----- - i p-p 2 ---------- + ?? ?? t d1 i m n ----- - i p-p 2 ---------- ? ?? ?? ?? t d2 + = (eq. 25) p up 1 , v in i m n ----- - i p-p 2 ---------- + ?? ?? t 1 2 ---- ?? ?? ?? f s (eq. 26) p up 2 , v in i m n ----- - i p-p 2 ---------- ? ?? ?? ?? t 2 2 ---- ?? ?? ?? f s (eq. 27) p up 3 , v in q rr f s = (eq. 28) p up 4 , r ds on () i m n ----- - ?? ?? ?? 2 d i p-p 2 12 ---------- d + (eq. 29) isl6334, isl6334a
26 fn6482.1 may 28, 2009 balance loop as well as setting the overcurrent trip point. select values for these resistors by using equation 30: where r isen is the sense resistor connected to the isen+ pin, n is the active channel number, r x is the resistance of the current sense element, either the dcr of the inductor or r sense depending on the sensing method, and i ocp is the desired overcurrent trip point. typically, i ocp can be chosen to be 1.2x the maximum load current of the specific application. with integrated temperature compensation, the sensed current signal is independent on the operational temperature of the power stage, i.e. the te mperature effect on the current sense element r x is cancelled by the integrated temperature compensation function. r x in equation 30 should be the resistance of th e current sense element at the room temperature. when the integrated temperat ure compensation function is disabled by pulling the tcomp pin to gnd, the sensed current will be dependent on t he operational te mperature of the power stage, since the dc resistance of the current sense element may be changed according to the operational temperature. r x in equation 30 should be the maximum dc resistance of the current sense element at the all operational temperature. in certain circumstances, it ma y be necessary to adjust the value of one or more isen resistors. when the components of one or more channels are inhibited from effectively dissipating their heat so that the affected channels run hotter than desired, choose new, sma ller values of risen for the affected phases (see the section entitled ?channel-current balance? on page 15). choose r isen,2 in proportion to the desired decrease in temperature rise in order to cause proportionally less current to flow in the hotter phase, as shown in equation 31: in equation 31, make sure that t 2 is the desired temperature rise above the ambient temperature, and t 1 is the measured temperature rise above the am bient temperature. while a single adjustment according to equation 31 is usually sufficient, it may occasionally be necessary to adjust r isen two or more times to achieve optimal thermal balance between all channels. load-line regulation resistor the load-line regulation resistor is labelled r fb in figure 6. its value depends on the desired loadline requirement of the application. the desired loadline can be calculated using equation 32: where i fl is the full load current of the specific application, and vr droop is the desired voltage droop under the full load condition. based on the desired loadline r ll , the loadline regulation resistor can be calcul ated using equation 33: where n is the active channel number, r isen is the sense resistor connected to the isen+ pin, and r x is the resistance of the current sens e element, either the dcr of the inductor or r sense depending on the sensing method. if one or more of the current sense resistors are adjusted for thermal balance (as in equation 31), the load-line regulation resistor should be selected ba sed on the average value of the current sensing resistors, as given in equation 34: where r isen(n) is the current sensing resistor connected to the n th isen+ pin. compensation the two opposing goals of compensating the voltage regulator are stability and speed. depending on whether the regulator employs the optional load-line regulation as described in load-line regulation, there are two distinct methods for achieving these goals. compensating load-line regulated converter the load-line regulated converter behaves in a similar manner to a peak-current mo de controller because the two poles at the output-filter l- c resonant frequency split with the introduction of current information into the control loop. the final location of these poles is determined by the system function, the gain of the current signal, and the value of the compensation components, r c and c c . since the system poles and zero are affected by the values of the components that are me ant to compensate them, the solution to the system equation becomes fairly complicated. fortunately there is a simple approximation that comes very close to an optimal solution. treating the system as though it were a voltage-mode regulator by compensating the l-c poles and the esr zero of t he voltage-mode approximation yields a solution that is always stable with very close to ideal transient performance. r isen r x 105 10 6 ? -------------------------- - i ocp n ------------- - = (eq. 30) r isen 2 , r isen t 2 t 1 ---------- = (eq. 31) r ll v droop i fl ------------------------ - = (eq. 32) r fb n r isen r ll r x --------------------------------- - = (eq. 33) r fb r ll r x ---------- r isen n () n = (eq. 34) isl6334, isl6334a
27 fn6482.1 may 28, 2009 the feedback resistor, r fb , has already been chosen as outlined in ?load-line regulation resistor? on page 26. select a target bandwidth fo r the compensated system, f 0 . the target bandwidth must be large enough to assure adequate transient performance, but smaller than 1/3 of the per-channel switching frequency. the values of the compensation components depend on the relationships of f 0 to the l-c pole frequency and the esr zero frequency. for each of the three cases which follow, there is a separate set of equations for the compensation components. in equation 35, l is the per-channel filter inductance divided by the number of active channels; c is the sum total of all output capacitors; esr is the equivalent-series resistance of the bulk output-filter capacitance; and v pp is the sawtooth amplitude described in the ?ele ctrical specifications? table beginning on page 8. the optional capacitor c 2 , is sometimes needed to bypass noise away from the pwm comparator. keep a position available for c 2 , and be prepared to install a high-frequency capacitor of between 10pf and 100pf in case any leading-edge jitter problem is noted. once selected, the compensation values in equation 35 assure a stable converter with reasonable transient performance. in mo st cases, transient performance can be improved by making adjustments to r c . slowly increase the value of r c while observing the transient performance on an oscilloscope until no further improvement is noted. normally, c c will not need adjustment. keep the value of c c from equation 35 unless some performance issue is noted. output filter design the output inductors and the ou tput capacitor bank together to form a low-pass filter responsible for smoothing the pulsating voltage at the phase nodes. the output filter also must provide the transient en ergy until the regulator can respond. because it has a low bandwidth compared to the switching frequency, the output filter necessarily limits the system transient response. th e output capacitor must supply or sink load current while the current in the output inductors increases or decreases to meet the demand. in high-speed converters, the out put capacitor bank is usually the most costly (and often the largest) part of the circuit. output filter design begins with minimizing the cost of this part of the circuit. the critical load parameters in choosing the output capacitors are the maximum size of the load step, i; the load-current slew rate, di/dt; and the maximum allowable output-voltage deviation under transient loading, v max . capacitors are characterized according to their capacitance, esr, and esl (equivalent series inductance). at the beginning of the load tr ansient, the output capacitors supply all of the transient current . the output voltage will initially deviate by an amount approximat ed by the voltage drop across the esl. as the load current increases, the voltage drop across the esr increases linearly until the load current reaches its final value. the capacitors selected must have sufficiently low esl and esr so that the total output-voltage deviation is less than the allowable maximum. neglecti ng the contribution of inductor current and regulator response, the output voltage initially deviates by an amount, as shown in equation 36: the filter capacitor must have sufficiently low esl and esr so that v < v max . most capacitor solutions rely on a mixture of high-frequency capacitors with relatively lo w capacitance in combination with bulk capacitors having high capacitance but limited high-frequency performance. minimizing the esl of the high-frequency capacitors allows them to support the output voltage as the current increases. minimizing the esr of the figure 17. compensation configuration for load-line regulated isl6334, isl6334a circuit isl6334, isl6334a comp c c r c r fb fb vdiff - + v droop c 2 (optional) 1 2 lc ------------------- f 0 > r c r fb 2 f 0 v p-p lc 0.75v in -------------------------------------- = c c 0.75v in 2 v p-p r fb f 0 ------------------------------------- = case 1: 1 2 lc ------------------- f 0 1 2 cesr () ----------------------------- - < r c r fb v p-p 2 () 2 f 0 2 lc 0.75 v in --------------------------------------------- - = c c 0.75v in 2 () 2 f 0 2 v p-p r fb lc -------------------------------------------------------------- = case 2: (eq. 35) f 0 1 2 c esr () ----------------------------- - > r c r fb 2 f 0 v p-p l 0.75 v in esr () ----------------------------------------- - = c c 0.75v in esr () c 2 v p-p r fb f 0 l ------------------------------------------------- = case 3: vesl () di dt ---- - esr () i + (eq. 36) isl6334, isl6334a
28 fn6482.1 may 28, 2009 bulk capacitors allows them to supply the increased current with less output voltage deviation. the esr of the bulk capacitors also creates the majority of the output-voltage ripple. as the bulk capacitors sink and source the inductor ac ripple current (see ?interleaving? on page 12 and equation 2), a voltage develops across the bulk-capacitor esr equal to i c(p-p ) (esr). thus, once the output capacitors are selected, the maximum allowable ripple voltage, v p-p(max) , determines the lower limit on the inductance, as shown in equation 37. since the capacitors are supplying a decreasing portion of the load current while the regulator recovers from the transient, the capacitor voltage becomes slightly depleted. the output inductors must be capable of assuming the entire load current before the output voltage decreases more than v max . this places an upper limit on inductance. equation 38 gives the upper limit on l for the cases when the trailing edge of the current transient causes a greater output-voltage deviation than the leading edge. equation 39 addresses the leading edge. normally, the trailing edge dictates the selection of l because duty cycles are usually less than 50%. nevertheless, both inequalities should be evaluated, and l should be selected based on the lower of the two results. in each equation, l is the per-channel inductance, c is the total output capacitance, and n is the number of active channels. switching frequency selection there are a number of variables to consider when choosing the switching frequency, as there are considerable effects on the upper-mosfet loss calculation. these effects are outlined in ?mosfets? on page 25, and they establish the upper limit for the switching frequency. the lower limit is established by the requirement for fast transient response and small output-voltage ripple as outlined in ?output filter design? on page 27. choose the lowest switching frequency that allows the regulator to meet the transient-response requirements. input capacitor selection the input capacitors are responsible for sourcing the ac component of the input current flowing into the upper mosfets. their rms current capa city must be sufficient to handle the ac component of the current drawn by the upper mosfets which is related to duty cycle and the number of active phases. for a 2-phase design, use figure 18 to determine the input-capacitor rms current requirement given the duty cycle, maximum sustai ned output current (i o ), and the ratio of the per-phase peak-to-peak inductor current (i l(p-p) ) to i o . select a bulk capacitor with a ripple current rating which will minimize the total number of input capacitors required to support the rms current calculated. the voltage rating of the capacitors should also be at least 1.25x greater than the maximum input voltage. figures 19 and 20 provide the same input rms current information for three and four phase designs respectively. use the same approach to selecting the bulk capacitor type and number as previously described. low capacitance, high-frequency ceramic capacitors are needed in addition to the bulk capacitors to suppress leading and falling edge voltage spikes. the result from the high current slew rates produced by the upper mosfets turn on and off. select low esl ceramic capacitors and place one as close as possible to each upper mosfet drain to minimize board parasitic impedances and maximize suppression. l esr () v in nv out ? ?? ?? v out f s v in v p-p max () ----------------------------------------------------------- - (eq. 37) l 2ncv o i () 2 --------------------- v max i esr () ? (eq. 38) l 1.25 () nc i () 2 ------------------------- - v max iesr () ? v in v o ? ?? ?? (eq. 39) 0.3 0.1 0 0.2 input-capacitor current (i rms /i o ) figure 18. normalized input-capacitor rms current vs duty cycle for 2-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v o /v in ) i l(p-p) = 0 i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o duty cycle (v o/ v in ) figure 19. normalized input-capacitor rms current vs duty cycle for 3-phase converter 00.4 1.0 0.2 0.6 0.8 input-capacitor current (i rms/ i o ) 0.3 0.1 0 0.2 i l(p-p) = 0 i l(p-p) = 0.25 i o i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o isl6334, isl6334a
29 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6482.1 may 28, 2009 multiphase rms improvement figure 21 is provided as a reference to demonstrate the dramatic reductions in input-c apacitor rms current upon the implementation of the multiphase topology. for example, compare the input rms current requirements of a 2-phase converter versus that of a single phase. assume both converters have a duty cycle of 0.25, maximum sustained output current of 40a, and a ratio of i l(p-p) to i o of 0.5. the single phase converter would require 17.3a rms current capacity while the 2-phase converter would only require 10.9a rms . the advantages become even more pronounced when output current is increased and additional phases are added to keep the component cost down relative to the single phase approach. layout considerations the following layout strategies are intended to minimize the impact of board parasitic impedances on converter performance and to optimize the heat-dissipating capabilities of the printed-circuit board. these sections highlight some important practices which should not be overlooked during the layout process. component placement within the allotted implementation area, orient the switching components first. the switching components are the most critical because they carry lar ge amounts of energy and tend to generate high levels of noise. switching component placement should take into account power dissipation. align the output inductors and mosfets such that space between the components is minimized while creating the phase plane. place the intersil mosf et driver ic as close as possible to the mosfets they control to reduce the parasitic impedances due to trace length between critical driver input and output signals. if possible, duplicate the same placement of these components for each phase. next, place the input and output capacitors. position one high-frequency ceramic input capacitor next to each upper mosfet drain. place the bulk i nput capacitors as close to the upper mosfet drains as dictated by the component size and dimensions. long distances between input capacitors and mosfet drains result in to o much trace inductance and a reduction in capacitor perf ormance. locate the output capacitors between the inductors and the load, while keeping them in close proximity to the microprocessor socket. voltage-regulator (vr) design materials the tolerance band calculation (tob) worksheets for vr output regulation and imon have been developed using the root-sum-squared (rss) method with 3 sigma distribution point of the related components and parameters. note that the ?electrical specificatio ns? table beginning on page 8 specifies no less than 6 sigma distribution point, not suitable for rss tob calculation. intersil also developed a set of worksheets to support vr design and layout. contact intersil?s local office or field support for the latest available information. input-capacitor current (i rms/ i o ) figure 20. normalized input-capacitor rms current vs duty cycle for 4-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v o/ v in ) 0.3 0.1 0 0.2 i l(p-p) = 0 i l(p-p) = 0.25 i o i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o figure 21. normalized input-capacitor rms current vs duty cycle for single-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v o/ v in ) input-capacitor current (i rms/ i o ) 0.6 0.2 0 0.4 i l(p-p) = 0 i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o isl6334, isl6334a
30 fn6482.1 may 28, 2009 isl6334, isl6334a package outline drawing l40.6x6 40 lead quad flat no-lead plastic package rev 3, 10/06 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (4x) 0.15 index area pin 1 a 6.00 b 6.00 31 36x 0.50 4.5 4x 40 pin #1 index area bottom view 40x 0 . 4 0 . 1 20 b 0.10 11 ma c 4 21 4 . 10 0 . 15 0 . 90 0 . 1 c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. detail "x" 0 . 05 max. 0 . 2 ref c 5 side view 1 10 30 typical recommended land pattern ( 5 . 8 typ ) ( 4 . 10 ) ( 36x 0 . 5 ) ( 40x 0 . 23 ) ( 40x 0 . 6 ) 6 6 top view 0 . 23 +0 . 07 / -0 . 05

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